US 12,451,172 B2
Memory device supporting parallel compression read operation and memory system including the same
Chan Keun Kwon, Gyeonggi-do (KR); and Hyeon Cheon Seol, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Aug. 30, 2023, as Appl. No. 18/458,152.
Claims priority of application No. 10-2023-0050058 (KR), filed on Apr. 17, 2023.
Prior Publication US 2024/0347082 A1, Oct. 17, 2024
Int. Cl. G11C 8/00 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01)
CPC G11C 7/1069 (2013.01) [G11C 7/222 (2013.01); G11C 2207/2281 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first memory region connected to first lines and configured to read data from the first memory region in response to a first clock;
a second memory region connected to second lines and configured to read data from the second memory region in response to a second clock;
a first transmission unit configured to:
compress the data read from the first memory region into first compression data, and
transmit, in response to the first clock, the first compression data through first selection lines among the first lines;
a second transmission unit configured to:
compress the data read from the second memory region into second compression data, and
transmit, in response to the second clock, the second compression data through second selection lines among the second lines; and
a first parallel transmission unit electrically connected to third lines, configured to:
simultaneously connect the first and second selection lines to the third lines,
select, as a selection clock, one having a lagging phase to the other between the first and second clocks, and
transmit the first and second compression data in parallel through the third lines in response to the selection clock.