US 12,451,171 B2
High-speed and area-efficient parallel-write-and-read memory
Hochul Lee, Los Angeles, CA (US); Anil Chowdary Kota, San Diego, CA (US); Dhvani Sheth, San Diego, CA (US); Bin Liang, San Diego, CA (US); and Chulmin Jung, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Jul. 10, 2023, as Appl. No. 18/349,918.
Prior Publication US 2025/0022494 A1, Jan. 16, 2025
Int. Cl. G11C 7/10 (2006.01); G11C 7/08 (2006.01)
CPC G11C 7/1069 (2013.01) [G11C 7/08 (2013.01); G11C 7/1012 (2013.01); G11C 7/1096 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A memory comprising:
a first bank of bitcells arranged into rows and columns;
a first bank column multiplexer configured to select a column from the first bank of bitcells;
a second bank of bitcells arranged into rows and columns;
a second bank column multiplexer configured to select a column from the second bank of bitcells;
an input/output circuit including a shared read path coupled to the first bank column multiplexer and to the second bank column multiplexer and including a shared write path coupled to the first bank column multiplexer and to the second bank column multiplexer; and
a controller configured to control a timing of a first read operation to the first bank of bitcells through the shared read path and to control a timing of a first write operation to the second bank of bitcells through the shared write path, wherein the first read operation is simultaneous with the first write operation.