US 12,451,170 B2
Dual reference ZQ calibration circuits and methods
Shiv Harit Mathur, Bangalore (IN)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Sandisk Technologies, Inc., Milpitas, CA (US)
Filed on Jul. 19, 2023, as Appl. No. 18/355,366.
Claims priority of provisional application 63/500,698, filed on May 8, 2023.
Prior Publication US 2024/0379138 A1, Nov. 14, 2024
Int. Cl. G11C 7/00 (2006.01); G11C 7/10 (2006.01); G11C 16/04 (2006.01)
CPC G11C 7/1048 (2013.01) [G11C 16/0483 (2013.01); G11C 2207/2254 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first pull-up driver circuit coupled to a first calibration node and a first input/output pad on an integrated circuit die;
a second pull-up driver circuit coupled to a second calibration node and a second input/output pad on the integrated circuit die;
a third pull-up driver circuit coupled to a third calibration node;
an internal resistor circuit coupled to the first calibration node;
a comparator comprising a first input terminal that may be selectively coupled to one of the first calibration node, the second calibration node and the third calibration node, and a second input terminal coupled to a reference voltage; and
circuitry configured to:
trim the reference voltage to compensate for an offset of the comparator; and
trim an impedance of the internal resistor circuit based on a comparison between a voltage on the first calibration node and the trimmed reference voltage,
wherein the trimmed impedance of the internal resistor circuit substantially equals a desired impedance of the third pull-up driver circuit
wherein the internal resistor circuit comprises a fixed resistor disposed in parallel with a coarse trim circuit and a fine trim circuit, and wherein:
the coarse trim circuit is configured to selectively perform a coarse trim of an impedance of the fixed resistor, and
the fine trim circuit is configured to selectively perform a fine trim of the impedance of the fixed resistor.