US 12,451,169 B2
Memory device including voltage and temperature sensing circuit and method for managing operation thereof
Poornima Venkatasubramanian, Bengaluru (IN); Gopi Sunanth Kumar Gogineni, Bengaluru (IN); Puneet Suri, Bengaluru (IN); Lava Kumar Pulluru, Bengaluru (IN); Karthikeyan Somashekara, Bengaluru (IN); and Manish Chandra Joshi, Bengaluru (IN)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 2, 2023, as Appl. No. 18/375,805.
Claims priority of application No. 202341021246 (IN), filed on Mar. 24, 2023; and application No. 202341021246 (IN), filed on Aug. 4, 2023.
Prior Publication US 2024/0321324 A1, Sep. 26, 2024
Int. Cl. G11C 7/04 (2006.01); G11C 5/14 (2006.01); G11C 7/12 (2006.01); G11C 7/14 (2006.01); G11C 7/22 (2006.01); G11C 8/16 (2006.01); G11C 11/417 (2006.01); G11C 11/419 (2006.01)
CPC G11C 7/04 (2013.01) [G11C 5/143 (2013.01); G11C 7/12 (2013.01); G11C 7/14 (2013.01); G11C 7/222 (2013.01); G11C 7/227 (2013.01); G11C 8/16 (2013.01); G11C 11/417 (2013.01); G11C 11/419 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a voltage and temperature sensing circuit configured to generate a Pull Down (PD) signal that varies based on upon at least one of a voltage and temperature at the memory device; and
primary pull down paths provided with secondary pull down paths, wherein the primary pull down paths are provided separately at a Dummy Read Bit line (DRBL) and a Dummy Global Read Bit line (DGRBL), wherein the secondary pull down paths are provided separately for the DRBL and the DGRBL parallel to the respective primary pull down paths,
wherein the voltage and temperature sensing circuit is configured to perform at least one of:
controlling at least one of the secondary pull down paths based on a voltage of the PD signal;
varying a discharge time of at least one of the dummy bit-lines based on the voltage of the PD signal; and
generating an early reset signal at one of a high temperature condition and a high voltage condition based on the voltage of the PD signal.