| CPC G11C 7/02 (2013.01) [G11C 7/1057 (2013.01); G11C 7/14 (2013.01)] | 20 Claims |
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1. A memory device, comprising:
a first pad;
a memory cell plane comprising a plurality of memory cells;
a page buffer circuit configured to:
sense the memory cell plane; and
identify, based on the sensing of the memory cell plane, a state stored in a memory cell of the plurality of memory cells, according to a ground voltage; and
a noise cancellation circuit configured to:
receive a first ground voltage from the first pad;
determine a reference voltage based on the first ground voltage;
generate a second ground voltage that offsets a noise voltage, based on the reference voltage; and
output the second ground voltage to the page buffer circuit.
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