| CPC G09G 3/3696 (2013.01) [G09G 2310/0294 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0209 (2013.01); G09G 2330/021 (2013.01)] | 18 Claims |

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1. A compensation circuit, comprising a timing controller, a power management circuit, an operational amplifier circuit, and a delay circuit,
wherein: the timing controller is respectively connected to a display panel and the delay circuit, and is configured to output a partial decode-and-forward (PDF) signal to the display panel and the delay circuit;
the power management circuit is respectively connected to the delay circuit and the operational amplifier circuit, and is configured to output a common voltage and an operating voltage to the delay circuit, and output the common voltage to the operational amplifier circuit;
the delay circuit is further connected to the operational amplifier circuit and the display panel respectively, and is configured to, when the display panel is controlled by the PDF signal to perform a polarity inversion, output the common voltage to the display panel in a first stage, and output the operating voltage to the operational amplifier circuit in a first sub-stage of the first stage, and stop outputting the operating voltage to the operational amplifier circuit in a second sub-stage of the first stage;
the delay circuit is further configured to, when the PDF signal controls the display panel not to perform the polarity inversion, output the operating voltage to the operational amplifier circuit in a second stage, and output the common voltage to the display panel in a third sub-stage of the second stage, and stop outputting the common voltage to the display panel in a fourth sub-stage of the second stage; and
the operational amplifier circuit is further connected to the display panel, and is configured to receive the common voltage output by the power management circuit in the first stage and the second stage; the operational amplifier circuit is further configured to receive the operating voltage output by the delay circuit and a feedback voltage output by the display panel in the first sub-stage, the third sub-stage and the fourth sub-stage, and output a compensating voltage to the display panel.
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