US 12,451,081 B2
Shift register, scanning driving circuit and displaying device
Jingwen Zhang, Beijing (CN); Yao Huang, Beijing (CN); and Binyan Wang, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and Beijing BOE Technology Development Co., Ltd., Beijing (CN)
Appl. No. 18/576,574
Filed by CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN); and BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD., Beijing (CN)
PCT Filed Apr. 28, 2023, PCT No. PCT/CN2023/091603
§ 371(c)(1), (2) Date Jan. 4, 2024,
PCT Pub. No. WO2024/221410, PCT Pub. Date Oct. 31, 2024.
Prior Publication US 2025/0095589 A1, Mar. 20, 2025
Int. Cl. G09G 3/3266 (2016.01); G11C 19/28 (2006.01); H10K 59/12 (2023.01)
CPC G09G 3/3266 (2013.01) [G11C 19/28 (2013.01); H10K 59/12 (2023.02); G09G 2310/0286 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A shift register, wherein the shift register comprises:
a first inputting circuit electrically connected to a start-signal terminal, a first node and a first clock-signal terminal, wherein the first inputting circuit is configured for, under control of a first clock signal of the first clock-signal terminal, writing a signal of the start-signal terminal into the first node;
a first outputting circuit electrically connected to the first node, an output terminal and a first voltage terminal, wherein the first outputting circuit is configured for, when switched on under control of a signal of the first node, writing a signal of the first voltage terminal into the output terminal;
a second inputting circuit electrically connected to the first node, a second node, a second voltage terminal and the first clock-signal terminal, wherein the second inputting circuit is configured for, under the control of the signal of the first node, writing the first clock signal into the second node, and, under the control of the first clock signal, writing a signal of the second voltage terminal into the second node;
a second outputting circuit electrically connected to a fourth voltage terminal, the second node and the output terminal, wherein the second outputting circuit is configured for, when switched on under control of a signal of the second node, writing a signal of the fourth voltage terminal into the output terminal; and
a second controlling circuit electrically connected to the first node, the second node, a fifth voltage terminal, a second clock-signal terminal and a controlling terminal, wherein the second controlling circuit is configured for, under the control of the signal of the second node, control of a second clock signal and control of a signal of the controlling terminal, when the first outputting circuit is switched on, disconnecting electric connection between the first node and the fifth voltage terminal, and when the second outputting circuit is switched on, writing a signal of the fifth voltage terminal into the first node,
wherein the second controlling circuit comprises a first sub-circuit and a second sub-circuit that are connected in series between the fifth voltage terminal and the first node,
the second sub-circuit is electrically connected to the controlling terminal, and the second sub-circuit is configured for, under the control of the signal of the controlling terminal, being disconnected when the first outputting circuit is switched on, and being switched on when the second outputting circuit is switched on,
the first sub-circuit is electrically connected to the second node and the second clock-signal terminal, and the first sub-circuit is configured for, when switched on under the control of the signal of the second node and the control of the second clock signal of the second clock-signal terminal, cooperating with the second sub-circuit to write the signal of the fifth voltage terminal into the first node, and
the controlling terminal is electrically connected to a fourth node.