| CPC G09G 3/3266 (2013.01) [G09G 3/2096 (2013.01); G09G 3/3233 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/0247 (2013.01); G09G 2320/045 (2013.01); G09G 2330/021 (2013.01); G09G 2330/12 (2013.01); G09G 2340/0435 (2013.01)] | 18 Claims |
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1. A scan driving circuit, comprising:
a plurality of scan stage circuits that each output a first carry signal and a scan signal; and
a plurality of sense stage circuits that each output a second carry signal and a sense signal, wherein
each of the plurality of scan stage circuits receives the first carry signal from at least one preceding or subsequent scan stage circuit,
each of the plurality of sense stage circuits receives the second carry signal from at least one preceding or subsequent sense stage circuit,
each of the plurality of sense stage circuits receives the first carry signal from one of the at least one preceding or subsequent scan stage circuit,
each of the plurality of scan stage circuits outputs the first carry signal and the scan signal based on a voltage of a first Q node,
each of the plurality of sense stage circuits outputs the second carry signal and the sense signal based on a voltage of a second Q node,
the plurality of scan stage circuits reset the voltage of the first Q node in response to a first reset signal, and
the plurality of sense stage circuits reset the voltage of the second Q node in response to a second reset signal that is different from the first reset signal.
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