| CPC G09G 3/3241 (2013.01) [G09G 3/3233 (2013.01); H10K 59/131 (2023.02); H10K 71/00 (2023.02); G09G 2300/0426 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0209 (2013.01); H10K 59/1201 (2023.02); H10K 59/1315 (2023.02)] | 15 Claims |
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1. A display substrate comprising: a substrate and a plurality of sub-pixels arrayed on the substrate, a data signal line pattern electrically connected to at least one of the plurality of sub-pixels, wherein the plurality of sub-pixels comprises:
a first sub-pixel and a second sub-pixel alternately arranged along a second direction;
the first sub-pixel and the second sub-pixel each comprises:
a power signal line pattern, at least part of the power signal line pattern extending along the second direction;
a power compensation pattern, at least part of the power compensation pattern extending along a first direction, wherein the power signal line pattern and the power compensation pattern are both located on a side of the data signal line pattern close to the substrate,
the power compensation pattern is electrically connected to power signal line patterns in two adjacent sub-pixels along the first direction; and
an orthographic projection of the power signal line pattern on the substrate at least partially does not overlap an orthographic projections of the data signal line pattern on the substrate;
wherein the first sub-pixel and the second sub-pixel each comprises:
a driving transistor, configured to drive a light emitting element to emit light;
a second transistor, electrically connected to the driving transistor and configured to initialize the driving transistor in response to control of a first scanning line;
a seventh transistor, electrically connected to the light emitting element and configured to initialize the light emitting element in response to control of a second scanning line;
a data writing transistor, electrically connected to the driving transistor and the data signal line pattern and configured to write a data signal into the driving transistor in response to control of a third scanning line; and
wherein the display substrate further comprises: an active layer located on the substrate and comprising:
a first active layer of the seventh transistor,
a second active layer of the second transistor, and
a third active layer of the data writing transistor;
a first conductive layer located on a side of the active layer away from the substrate and comprising: the data signal line pattern extending in the second direction; and
a first gate metal layer located on the substrate and comprising: a gate electrode of the driving transistor;
wherein the gate electrode of the driving transistor is electrically connected to a first conductive region of the second active layer;
the data signal line pattern is electrically connected to a first conductive region of the third active layer;
an orthographic projection of the second active layer of the second transistor of the first sub-pixel on the substrate is a second orthographic projection, an orthographic projection of the first active layer of the seventh transistor of the second sub-pixel on the substrate is a first orthographic projection, an orthographic projection of the data signal line pattern corresponding to at least one of the plurality of sub-pixels on the substrate is a third orthographic projection, and the second orthographic projection is between the first orthographic projection and the third orthographic projection.
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