| CPC G09G 3/3233 (2013.01) [G09G 3/3266 (2013.01); G11C 19/28 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0247 (2013.01); G09G 2320/10 (2013.01)] | 19 Claims |
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1. A display panel, comprising:
a plurality of pixel driving circuits, comprising:
a driving circuit, connected to a first node, a second node, and a third node, and configured to input, in response to a signal from the first node, a driving current to the third node through the second node, and
a first switching unit, having a first terminal connected to the third node and a second terminal connected to a sensing signal terminal, and configured to electrically connect, in response to a signal at a control terminal of the first switching unit, the third node and the sensing signal terminal; and
a first gate driving circuit, comprising a plurality of first output terminals, the first output terminal being provided to correspond to the pixel driving circuit, and being connected to the control terminal of the first switching unit in the pixel driving circuit corresponding to the first output terminal,
wherein a driving cycle of the pixel driving circuit comprises a data writing stage, a plurality of light-emitting stages, and a black frame insertion stage provided between adjacent light-emitting stages, and the first output terminal is configured to output an active level pulse during the data writing stage and the black frame insertion stage of the pixel driving circuit corresponding to the first output terminal,
wherein the first gate driving circuit comprises a plurality of first shift register units in cascade connection, and the first shift register unit comprises:
a first input circuit, connected to a first power supply terminal, a first clock signal terminal, a fourth node, a fifth node, a second clock signal terminal, and configured to transmit, in response to a signal from the first clock signal terminal, a signal from the first power supply terminal to the fourth node, and transmit, in response to a signal from the fourth node, a signal from the second clock signal terminal to the fifth node;
a second input circuit, connected to the first power supply terminal, the first clock signal terminal, a first signal input terminal, a second power supply terminal and a sixth node, and configured to transmit, in response to the signal from the first clock signal terminal, the signal from the first power supply terminal to the sixth node, and transmit, in response to a signal from the first signal input terminal and the signal from the first clock signal terminal, a signal from the second power supply terminal to the sixth node;
a first output circuit, connected to the sixth node, a seventh node, the first power supply terminal, a first signal output terminal and the second power supply terminal, and configured to transmit, in response to a signal from the sixth node, the signal from the second power supply terminal to the first signal output terminal, and transmit, in response to a signal from the seventh node, the signal from the first power supply terminal to the first signal output terminal, wherein the seventh node is connected to the fifth node;
a first pull-down circuit, connected to the seventh node, the sixth node, the second power supply terminal and the fourth node, and configured to transmit, in response to the signal from the sixth node, the signal from the second power supply terminal to the seventh node and the fourth node; and
a second pull-down circuit, connected to the fourth node, the sixth node, the second clock signal terminal and the second power supply terminal, and configured to transmit, in response to the signal from the fourth node and the signal from the second clock signal terminal, the signal from the second power supply terminal to the sixth node, and
wherein the first signal output terminal of the first shift register unit forms the first output terminal of the first gate driving circuit.
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