| CPC G09G 3/3208 (2013.01) [G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/0247 (2013.01)] | 20 Claims |
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1. A display panel, comprising:
a display region; and
bias signal lines and a plurality of rows of pixel circuits;
wherein a pixel circuit among the plurality of rows of pixel circuits comprises a drive module and a bias module; the drive module is configured to drive a light-emitting element; and the bias module is connected between a first terminal of the drive module and a bias signal line among the bias signal lines, and the bias module is configured to write a voltage on the bias signal line to the first end of the drive module when the bias module is turned on;
wherein the display region comprises a first display region and a second display region; the bias signal lines comprise a first bias signal line and a second bias signal line; bias modules in the first display region are connected to the first bias signal line; bias modules in the second display region are connected to the second bias signal line; and in at least part of turn-on stages of bias modules, a voltage transmitted by the first bias signal line is different from a voltage transmitted by the second bias signal line;
wherein the bias module is configured to be turned on at a first bias stage and at a second bias stage; and
the bias signal line is configured to input a first bias voltage at the first bias stage of each row of pixel circuits in a corresponding display region and input a second bias voltage at the second bias stage of the each row of pixel circuits in the corresponding display region, wherein the each row of pixel circuits are among the plurality of rows of pixel circuits;
wherein a display period of the display panel comprises a first display stage and a second display stage, the first bias stage is located at the first display stage, the second bias stage is located at the second display stage, the first display stage has i first bias stages, the second display stage has j second bias stages, and i and j are each an integer greater than or equal to 1; and
wherein a control terminal of the bias module is connected with a first scan signal, the first scan signal comprises i first turning-on levels located at the first display stage and j second turning-on levels located at the second display stage, and the bias module is configured to be turned on at the first bias stages in response to the first turning-on levels in the first scan signal and is configured to be turned on at the second bias stages in response to the second turning-on levels in the first scan signal; and
the bias signal line is further configured to:
input the first bias voltage during a period from a start of a first one of the first turning-on levels of the first scan signal connected to the first row of pixel circuits in the corresponding display region to an end of an i-th one of the first turning-on levels of the first scan signal connected to the last row of pixel circuits in the corresponding display region; and
input the second bias voltage during a period from a start of a first one of the second turning-on levels of the first scan signal connected to the first row of pixel circuits in the corresponding display region to an end of a j-th one of the second turning-on levels of the first scan signal connected to the last row of pixel circuits in the corresponding display region.
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