US 12,451,045 B2
Gate driver on array circuit
Xiaowen Lv, Guangdong (CN)
Assigned to TCL China Star Optoelectronics Technology Co., Ltd., Shenzhen (CN)
Appl. No. 17/598,889
Filed by TCL China Star Optoelectronics Technology Co., Ltd., Guangdong (CN)
PCT Filed Jul. 28, 2021, PCT No. PCT/CN2021/108789
§ 371(c)(1), (2) Date May 22, 2024,
PCT Pub. No. WO2023/000357, PCT Pub. Date Jan. 26, 2023.
Claims priority of application No. 202110812274.0 (CN), filed on Jul. 19, 2021.
Prior Publication US 2024/0312387 A1, Sep. 19, 2024
Int. Cl. G09G 3/20 (2006.01)
CPC G09G 3/2092 (2013.01) [G09G 2310/0267 (2013.01); G09G 2310/08 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A gate driver on array (GOA) circuit, comprising a first GOA unit and a plurality of second GOA units, the first GOA unit and the plurality of second GOA units are cascaded,
wherein the first GOA circuit comprises:
a first pull-up control module, comprising:
a first transistor, having a gate receiving a control signal, a source receiving a starting signal, and a drain electrically connected to a first node;
wherein when the first transistor is turned off, a voltage level of the gate of the first transistor is lower than a voltage level of the source; the source of the first transistor is an end for signal inputting; and the drain of the first transistor is an end for signal outputting,
wherein each of the plurality of second GOA units comprises:
a second pull-up control module, comprising:
a second transistor, having a gate receiving a (N−M)th-stage stage signal, a source receiving a (N−M)th-stage scan signal, and a drain electrically connected to a second node;
wherein the second GOA unit further comprises:
a second pull-up module, electrically connected to the second node, a stage signal output end of a current stage and a scan signal output end of the current stage, configured to receive a high-frequency clock signal and output a stage signal of the current stage and a scan signal of the current stage under a control of a voltage level of the second node;
a second pull-down module, electrically connected to the second node, configured to receive the (N+M) th-stage scan signal and the first low reference signal and to pull down a voltage level of the second node under a control of the (N+M) th-stage scan signal and the first low reference signal; and
a second pull-down maintaining module, electrically connected to the second node and the scan signal output end of the current stage, configured to receive a first low-frequency clock signal, a second low-frequency clock signal, the first low reference signal and a second low reference signal and to maintain the voltage level of the second node and a voltage level of the scan signal of the current stage as a voltage level of the first low reference signal after the pull-down module pulls down the voltage level of the second node;
wherein M and N are integers and N is greater than M.