US 12,451,041 B2
Display panel and display device
Zongcai Ding, Xiamen (CN); Xuhui Peng, Xiamen (CN); Weiqiang Wu, Xiamen (CN); Jie Lin, Xiamen (CN); Xiaohe Li, Xiamen (CN); and Qiongqin Mao, Xiamen (CN)
Assigned to Xiamen Tianma Optoelectronics Co., Ltd., Xiamen (CN)
Filed by Xiamen Tianma Optoelectronics Co., Ltd., Xiamen (CN)
Filed on Oct. 23, 2024, as Appl. No. 18/924,244.
Claims priority of application No. 202410199837.7 (CN), filed on Feb. 22, 2024.
Prior Publication US 2025/0046225 A1, Feb. 6, 2025
Int. Cl. G09G 3/20 (2006.01); G06F 3/041 (2006.01); G11C 19/28 (2006.01)
CPC G09G 3/20 (2013.01) [G06F 3/04166 (2019.05); G11C 19/28 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2354/00 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A display panel, comprising:
a first drive circuit comprising a plurality of shift registers,
wherein at least one shift register of the plurality of shift registers is a first-type shift register; and
the first-type shift register comprises a pull-up unit, a voltage storage unit, and a first output unit, wherein
the pull-up unit is connected to a first trigger terminal, a first signal terminal, and a first node, and the pull-up unit is configured to, in response to control of the first trigger terminal, adjust a signal of the first node according to a signal of the first signal terminal;
the voltage storage unit is connected to the first node, a first clock terminal, a second signal terminal, a third signal terminal, a fourth signal terminal, and a second node, and the pull-up unit is configured to, in response to control of the first node and control of the first clock terminal, adjust a signal of the second node or store the signal of the second node according to a signal of the second signal terminal, a signal of the third signal terminal, and a signal of the fourth signal terminal; and
the first output unit is connected to the second node, the first clock terminal, and an output terminal and configured to, in response to control of the second node, adjust a signal of the output terminal according to a signal of the first clock terminal;
wherein the voltage storage unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor;
a gate of the first transistor is connected to the first node, and the first transistor is connected between the third signal terminal and a gate of the third transistor;
a gate of the second transistor is connected to the first clock terminal, and the second transistor is connected between the second signal terminal and the gate of the third transistor;
the third transistor is connected between the fourth signal terminal and a gate of the fourth transistor;
the fourth transistor is connected between the gate of the fourth transistor and the second node;
the first capacitor is coupled between the gate of the third transistor and the gate of the fourth transistor; and
wherein the display panel comprises at least one of the following:
wherein a channel width-to-length ratio of the first transistor is F1, and a channel width-to-length ratio of the second transistor is F2, and wherein F1 is greater than F2; or,
wherein a channel width-to-length ratio of the second transistor is F2, and a channel width-to-length ratio of the third transistor is F3, and wherein F2=F3.