US 12,450,814 B2
Dynamic tile sequencing in graphic processing
Subramaniam Maiyuran, Gold River, CA (US); Jorge F. Garcia Pabon, Folsom, CA (US); Raghavendra Kamath Miyar, Bangalore (IN); Sudheendra Srivathsa, Bangalore (IN); and Krishan Malik, Bangalore (IN)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 24, 2021, as Appl. No. 17/485,017.
Prior Publication US 2023/0095535 A1, Mar. 30, 2023
Int. Cl. G06T 1/20 (2006.01); G06T 1/60 (2006.01); G06T 15/00 (2011.01)
CPC G06T 15/005 (2013.01) [G06T 1/20 (2013.01); G06T 1/60 (2013.01)] 20 Claims
OG exemplary drawing
 
8. A method comprising:
receiving data for rendering of a render target, the render target including a plurality of tiles; and
performing tile sequencing between a hashing table and the render target to map the plurality of tiles of the render target to a plurality of portions of processing circuitry of a computing device;
wherein the tile sequencing is performed according to a mode selected from a plurality of modes for tile sequencing, the plurality of modes providing for selection for the hashing table utilized in tile sequencing, the plurality of modes including:
a first mode for tile sequencing, wherein tile sequencing in the first mode includes a set granularity for entries of the hashing table; and
a second mode for tile sequencing, wherein tile sequencing in the second mode includes a configurable granularity for entries of the hashing table.