US 12,450,698 B2
Joint denoising and supersampling of graphics data
Manu Mathew Thomas, Sunnyvale, CA (US); Karthik Vaidyanathan, San Francisco, CA (US); Anton Kaplanyan, Mercer Island, WA (US); SungYe Kim, Folsom, CA (US); and Gabor Liktor, San Francisco, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 30, 2022, as Appl. No. 17/958,211.
Claims priority of provisional application 63/276,257, filed on Nov. 5, 2021.
Prior Publication US 2023/0148225 A1, May 11, 2023
Int. Cl. G06T 5/70 (2024.01); G06F 18/213 (2023.01); G06T 1/20 (2006.01); G06T 3/18 (2024.01); G06T 3/4046 (2024.01); G06T 3/4053 (2024.01); G06T 5/20 (2006.01); G06T 15/06 (2011.01)
CPC G06T 5/70 (2024.01) [G06F 18/213 (2023.01); G06T 1/20 (2013.01); G06T 3/18 (2024.01); G06T 3/4046 (2013.01); G06T 3/4053 (2013.01); G06T 5/20 (2013.01); G06T 15/06 (2013.01); G06T 2210/36 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A graphics processor comprising:
a plurality of processing resources, including a least a first processing resource including a pipeline to perform a supersampling operation; and
the pipeline including circuitry to jointly perform denoising and supersampling of received ray tracing input data in a single neural network, the circuitry including:
first circuitry to receive input data associated with an input block for the neural network and to upsample the received input data from a first resolution to a second resolution,
second circuitry to perform operations associated with a feature extraction and kernel prediction network of the neural network, the feature extraction and kernel prediction network including operation of a single shared feature extractor for the neural network, and
third circuitry to perform operations associated with a filtering block of the neural network.