| CPC G06T 1/60 (2013.01) [G06F 12/08 (2013.01); G06T 11/40 (2013.01); G06T 15/005 (2013.01)] | 18 Claims |
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1. A multicore graphics rendering system, comprising a plurality of cores configured to implement tile-based rendering of a stream of primitives,
wherein first cores of the plurality of cores are configured to perform geometry processing work, and second cores of the plurality of cores are configured to perform fragment processing work,
wherein each first core is configured to process groups of primitives, to produce transformed geometry data describing, for each of a plurality of tiles, the primitives processed by that first core that are present in that tile, each group being associated with a group index, the group indices defining an ordering of the groups in the stream of primitives,
the first cores being configured to store in a memory the transformed geometry data that they produce,
each second core being configured to perform fragment processing for one or more of the tiles, wherein each second core is configured to, for each tile to be processed, read from the memory the transformed geometry data produced by the first cores for that tile,
wherein one of the plurality of cores comprises an allocation manager, configured to allocate portions of the memory to the first cores to store the transformed geometry data,
wherein the multicore graphics rendering system uses at least one virtualised memory space, wherein each of the plurality of cores comprises a memory management unit (MMU), configured to translate between virtual memory portions in the at least one virtualised memory space and physical memory portions of the memory,
wherein the allocation manager is configured to allocate for the MMUs a hierarchical index, to index the physical memory portions associated with the virtual memory portions in the at least one virtualised memory space,
wherein the allocation manager is configured to segment the virtualised memory space such that the first cores are allocated respective non-overlapping virtual address ranges in the space, the virtual address ranges being associated with different entries in a top level of the hierarchical index,
wherein the allocation manager is configured to, before the geometry processing work for a frame begins, pre-allocate the top level of the hierarchical index, and prime each MMU by providing the MMU with said top level of the hierarchical index, and
wherein the transformed geometry data produced by each first core comprises:
a set of tile control lists, describing for each tile, the primitives processed by that first core that are present in that tile;
a head pointer for each tile control list, wherein the head pointer points to the start of the respective tile control list; and
one or more primitive blocks, containing data describing the primitives;
wherein the tile control lists contain pointers to the one or more primitive blocks.
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