US 12,450,680 B2
Out-of-order execution of graphics processing unit texture sampler operations
Carlos Nava Rodriguez, Folsom, CA (US); Benjamin Pletcher, Mather, CA (US); Yoav Harel, Carmichael, CA (US); Bret Martin, Folsom, CA (US); and Sudarshanram Shetty, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 24, 2021, as Appl. No. 17/484,619.
Prior Publication US 2023/0111571 A1, Apr. 13, 2023
Int. Cl. G06T 1/20 (2006.01); G06T 1/60 (2006.01); G06T 15/04 (2011.01)
CPC G06T 1/20 (2013.01) [G06T 1/60 (2013.01); G06T 15/04 (2013.01)] 21 Claims
OG exemplary drawing
 
15. A texture sampler of a graphics processing unit, the texture sampler comprising:
a latency queue operable to store information regarding a set of transactions associated with each of a plurality of texture sampler operations; and
a plurality of virtual channel (VC) queues each operable to store information regarding transactions for a respective single texture sampler operation at a time, wherein the texture sampler is operable to, during a transaction processing interval, facilitate out-of-order processing of the plurality of texture sampler operations by:
determining availability of data in a level 1 (L1) cache associated with the texture sampler for the transactions associated with each of the plurality of VC queues;
selecting a VC queue of the plurality of VC queues based on the determined availability of data including prioritizing a particular VC queue of the plurality of VC queues containing information regarding transactions representing all transactions for the respective single texture sampler operation over another VC queue of the plurality of VC queues containing information regarding transactions representing less than all transactions for the respective single texture sampler operation; and
processing a transaction associated with a head of the selected VC queue.