| CPC G06N 3/04 (2013.01) [G06F 30/27 (2020.01); G06F 30/36 (2020.01); G06F 30/373 (2020.01); G06N 3/045 (2023.01); G06N 3/08 (2013.01); G06N 3/084 (2013.01); G06F 30/00 (2020.01); G06F 2119/06 (2020.01)] | 26 Claims |
|
1. A method, comprising:
at one or more devices that implement a neural network having a convolutional neural network (CNN) layer and a regression layer, wherein the neural network is trained to predict per-cell IR drop from a plurality of given power maps for a given circuit design, and wherein the neural network is trained using a learning set of existing circuit partitions with known IR drop information, and that implement a circuit design tool:
receiving a plurality of power maps for a circuit design at the neural network;
processing the plurality of power maps, by the CNN layer of the neural network, to predict a plurality of coefficient maps that include weight factors for a plurality of cells of the circuit design;
processing the plurality of coefficient maps together with cell-level features for the plurality of cells of the circuit design, by the regression layer of the neural network, to predict an IR drop for each of the plurality of cells in the circuit design;
modifying at least one of a cell layout of the circuit design or a power distribution of the circuit design, via the circuit design tool, to improve at least one of a timing or a functionality of the circuit design, based on the IR drop predicted for each of the plurality of cells in the circuit design, wherein the modifying results in an improved circuit design; and
wherein a physical circuit is generated in accordance with the improved circuit design including at least:
placing a plurality of transistors on a circuit board in accordance with the cell layout of the improved circuit design, and
creating power distribution pathways in accordance with the power distribution of the circuit design.
|