US 12,450,418 B2
Semiconductor layout in FinFET technologies
Farzan Farbiz, Mountain View, CA (US); Thomas Hoffmann, Los Gatos, CA (US); and Xin Yi Zhang, Cupertino, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jun. 20, 2023, as Appl. No. 18/337,781.
Application 18/337,781 is a continuation of application No. 16/920,524, filed on Jul. 3, 2020, granted, now 11,720,734.
Application 16/920,524 is a continuation of application No. 15/697,239, filed on Sep. 6, 2017, granted, now 10,740,527, issued on Aug. 1, 2020.
Prior Publication US 2023/0409797 A1, Dec. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/394 (2020.01); G06F 30/33 (2020.01); G06F 30/39 (2020.01); G06F 30/392 (2020.01); H10D 30/62 (2025.01); H10D 84/85 (2025.01); H10D 84/90 (2025.01); H10D 89/60 (2025.01)
CPC G06F 30/392 (2020.01) [G06F 30/33 (2020.01); G06F 30/39 (2020.01); G06F 30/394 (2020.01); H10D 30/62 (2025.01); H10D 84/854 (2025.01); H10D 84/907 (2025.01); H10D 84/991 (2025.01); H10D 89/601 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a plurality of power rails, comprising at least a first power rail and a second power rail, individually connected to different power supplies;
a well formed in a substrate;
one or more active devices formed in the well;
a well tap cell placed adjacent to one of the one or more active devices, wherein:
the well tap cell comprises two high-dopant regions connected to the first power rail with a transistor gate stripe between the two high-dopant regions connected to the second power rail; and
the transistor gate stripe has a first work function less than a second work function of transistor gate stripes of the one or more active devices to increase a decoupling capacitance below the transistor gate stripe between the first power rail and the second power rail.