US 12,450,417 B2
Semiconductor metal layer structure over cell region
Shang-Hsuan Chiu, Hsinchu (TW); Chih-Liang Chen, Hsinchu (TW); Hui-Zhong Zhuang, Kaohsiung (TW); Chi-Yu Lu, New Taipei (TW); and Jerry Chang Jui Kao, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 1, 2022, as Appl. No. 17/856,412.
Claims priority of provisional application 63/268,779, filed on Mar. 2, 2022.
Prior Publication US 2023/0281373 A1, Sep. 7, 2023
Int. Cl. G06F 30/392 (2020.01); G06F 30/396 (2020.01); H01L 21/027 (2006.01); H01L 21/68 (2006.01); H01L 21/71 (2006.01); H01L 23/52 (2006.01); H01L 25/00 (2006.01); H03K 19/00 (2006.01); G06F 119/18 (2020.01)
CPC G06F 30/392 (2020.01) [G06F 30/396 (2020.01); G06F 2119/18 (2020.01); H01L 21/027 (2013.01); H01L 21/68 (2013.01); H01L 21/71 (2013.01); H01L 23/52 (2013.01); H01L 25/00 (2013.01); H03K 19/00 (2013.01)] 20 Claims
OG exemplary drawing
 
15. A method of forming a cell layout structure, the method comprising:
forming a metal diffusion (MD) layer and gates over an active region of one or more cells;
forming a first metallization layer including MD tracks over the one or more cells; and
forming a second metallization layer including M1 tracks over the first metallization layer, wherein first M1 tracks are disposed a first predetermined distance from an edge of a cell, wherein second M1 tracks are disposed a second predetermined distance from the edge of the cell, wherein the first M1 tracks are longer than the second M1 tracks, and wherein the first predetermined distance is smaller than the second predetermined distance.