US 12,450,416 B2
Integrated circuit and method of forming the same
Johnny Chiahao Li, Hsinchu (TW); Jung-Chan Yang, Hsinchu (TW); Jian-Sing Li, Hsinchu (TW); Hui-Zhong Zhuang, Hsinchu (TW); Jerry Chang Jui Kao, Hsinchu (TW); and Xiangdong Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 23, 2022, as Appl. No. 17/821,559.
Claims priority of provisional application 63/346,033, filed on May 26, 2022.
Prior Publication US 2023/0385504 A1, Nov. 30, 2023
Int. Cl. G06F 30/30 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H10D 84/90 (2025.01); H10D 89/10 (2025.01)
CPC G06F 30/392 (2020.01) [G06F 30/394 (2020.01); H10D 84/907 (2025.01); H10D 89/10 (2025.01); H10D 84/914 (2025.01); H10D 84/975 (2025.01); H10D 84/985 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming an integrated circuit (IC), the method comprising:
generating, by a processor, a netlist of a first circuit, wherein the first circuit is configured as a non-functional circuit, and the first circuit includes a first pin and a second pin that are electrically disconnected from each other, wherein generating the netlist of the first circuit comprises:
designating the first pin and the second pin as a first group of pins that are to be connected together;
generating, by the processor, a first cell layout of the first circuit, wherein the first cell layout includes a first conductive feature pattern and a second conductive feature pattern extending in a first direction, being on a first layout level, and being separated from each other in a second direction different from the first direction, wherein the first conductive feature pattern and the second conductive feature pattern are not coupled together, the first conductive feature pattern corresponds to the first pin, and the second conductive feature pattern corresponds to the second pin;
placing the first cell layout, by an automatic placement and routing (APR) tool, in a first region of a layout design, wherein placing the first cell layout by the APR tool comprises:
connecting the first pin and the second pin in the first group of pins together thereby changing the first circuit to a second circuit, the second circuit being configured as a functional version of the first circuit.