US 12,450,414 B2
Systems and methods for generating placements for circuit designs using pyramidal flows
Alexander Andreev, San Jose, CA (US); Alexander Rusakov, Moscow (RU); and Alexander Yakhontov, Moscow (RU)
Assigned to Altera Corporation, San Jose, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 20, 2021, as Appl. No. 17/556,911.
Prior Publication US 2022/0114321 A1, Apr. 14, 2022
Int. Cl. G06F 30/392 (2020.01); G06F 111/04 (2020.01)
CPC G06F 30/392 (2020.01) [G06F 2111/04 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method for using an integrated circuit placement tool to place a circuit design for an integrated circuit, the method comprising:
generating a graph comprising objects and targets in a first level of a pyramid;
generating clusters of objects in a second level of the pyramid in each of the objects in the first level, wherein the second level is different than the first level;
generating clusters of targets in the second level in each of the targets in the first level, wherein the objects in the first and the second levels comprise circuit blocks in the circuit design, and wherein the targets in the first and the second levels comprise subregions of the integrated circuit; and
generating first flows from the objects in the second level to the targets in the second level for an output placement of the circuit blocks that satisfies at least one constraint of the integrated circuit.