US 12,450,411 B2
Hazard generating for speculative cores in a microprocessor
Shakti Kapoor, Austin, TX (US); Nelson Wu, Austin, TX (US); and Manoj Dusanapudi, Bangalore (IN)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Dec. 17, 2021, as Appl. No. 17/554,821.
Prior Publication US 2023/0195981 A1, Jun. 22, 2023
Int. Cl. G06F 30/33 (2020.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 12/0891 (2016.01); G06F 115/10 (2020.01)
CPC G06F 30/33 (2020.01) [G06F 9/30058 (2013.01); G06F 9/3851 (2013.01); G06F 12/0891 (2013.01); G06F 9/3806 (2013.01); G06F 9/3818 (2013.01); G06F 2115/10 (2020.01); G06F 2212/1008 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for generating a hazard in a processor, the method comprising:
identifying one or more cache lines to invalidate in a second level memory of a processing core in the processor;
invalidating, in response to identifying the one or more cache lines to invalidate in the second level memory, the one or more identified cache lines in the second level memory; and
invalidating, in response to invalidating the one or more identified cache lines in the second level memory, the corresponding one or more cache lines in a first level memory.