US 12,450,191 B2
Methods and apparatus for providing a serializer and deserializer (serdes) block facilitating high-speed data transmissions for a field-programmable gate array (FPGA)
Grant Thomas Jennings, Austin, TX (US)
Assigned to Gowin Semiconductor Corporation, GuangZhou (CN)
Filed by GOWIN Semiconductor Corporation, GuangZhou (CN)
Filed on Jan. 16, 2024, as Appl. No. 18/414,403.
Application 18/414,403 is a continuation of application No. 17/968,646, filed on Oct. 18, 2022, granted, now 11,874,792.
Application 17/968,646 is a continuation of application No. 17/318,841, filed on May 12, 2021, granted, now 11,474,969.
Prior Publication US 2024/0152484 A1, May 9, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/42 (2006.01); G06F 1/08 (2006.01); H03K 19/17736 (2020.01); H03M 5/04 (2006.01); H03M 9/00 (2006.01)
CPC G06F 13/4291 (2013.01) [G06F 1/08 (2013.01); H03K 19/17744 (2013.01); H03M 5/04 (2013.01); H03M 9/00 (2013.01); G06F 2213/0042 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus for network communication containing a programmable device able to perform user configurable logic functions, comprising:
a field-programmable gate array (“FPGA”) containing a first input deserializer configured to obtain a first sample on P-channel of a Universal Serial Bus (“USB”) bus in accordance with a first clock frequency, and a second input deserializer configured to obtain second samples on N-channel of USB bus in accordance with a second clock frequency; and
a sample decoder coupled to the first input deserializer and configured to generate decoded data in response to the first and second samples.