US 12,450,178 B2
Aggregation of multiple memory modules for a system-on-chip
Anwar Ali, San Jose, CA (US); James Church, West Linn, OR (US); and Gokulnath Sulur, Santa Clara, CA (US)
Assigned to Avago Technologies International Sales Pte. Limited, Singapore (SG)
Filed by Avago Technologies International Sales Pte. Limited, Singapore (SG)
Filed on Oct. 4, 2023, as Appl. No. 18/480,832.
Claims priority of provisional application 63/505,928, filed on Jun. 2, 2023.
Prior Publication US 2024/0403235 A1, Dec. 5, 2024
Int. Cl. G06F 12/00 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01)
CPC G06F 13/1657 (2013.01) [G06F 13/1678 (2013.01); G06F 13/4068 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A system comprising:
a substrate comprising a first circuit;
a second circuit formed in a first die disposed on the substrate, the second circuit comprising at least a processor and a first memory interface, the first memory interface being disposed in a first edge of the first die and being configured to couple the processor with the first circuit, the second circuit comprising a graphic processing unit (GPU);
a third circuit formed in a second die disposed on the substrate adjacent to the first edge of the first die, the third circuit comprising a second memory interface configured to couple to the first circuit; and
multiple memory modules disposed on the second die, each of the multiple memory modules at least partially sharing the second memory interface to communicate with the processor via the first circuit and the first memory interface.