US 12,450,177 B2
Dynamic buffer management in data-driven intelligent network
Abdulla M. Bataineh, Vista, CA (US); Timothy J. Johnson, Sun Prairie, WI (US); and Jonathan P. Beecroft, Bristol (GB)
Assigned to Hewlett Packard Enterprise Development LP, Spring, TX (US)
Appl. No. 17/594,780
Filed by Hewlett Packard Enterprise Development LP, Houston, TX (US)
PCT Filed Mar. 23, 2020, PCT No. PCT/US2020/024239
§ 371(c)(1), (2) Date Oct. 29, 2021,
PCT Pub. No. WO2020/236267, PCT Pub. Date Nov. 26, 2020.
Claims priority of provisional application 62/852,273, filed on May 23, 2019.
Claims priority of provisional application 62/852,203, filed on May 23, 2019.
Claims priority of provisional application 62/852,289, filed on May 23, 2019.
Prior Publication US 2022/0200923 A1, Jun. 23, 2022
Int. Cl. G06F 13/16 (2006.01); G06F 9/50 (2006.01); G06F 9/54 (2006.01); G06F 12/0862 (2016.01); G06F 12/1036 (2016.01); G06F 12/1045 (2016.01); G06F 13/14 (2006.01); G06F 13/28 (2006.01); G06F 13/38 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G06F 15/173 (2006.01); H04L 1/00 (2006.01); H04L 43/0876 (2022.01); H04L 43/10 (2022.01); H04L 45/00 (2022.01); H04L 45/02 (2022.01); H04L 45/021 (2022.01); H04L 45/028 (2022.01); H04L 45/12 (2022.01); H04L 45/122 (2022.01); H04L 45/125 (2022.01); H04L 45/16 (2022.01); H04L 45/24 (2022.01); H04L 45/42 (2022.01); H04L 45/745 (2022.01); H04L 47/10 (2022.01); H04L 47/11 (2022.01); H04L 47/12 (2022.01); H04L 47/122 (2022.01); H04L 47/20 (2022.01); H04L 47/22 (2022.01); H04L 47/24 (2022.01); H04L 47/2441 (2022.01); H04L 47/2466 (2022.01); H04L 47/2483 (2022.01); H04L 47/30 (2022.01); H04L 47/32 (2022.01); H04L 47/34 (2022.01); H04L 47/52 (2022.01); H04L 47/62 (2022.01); H04L 47/625 (2022.01); H04L 47/6275 (2022.01); H04L 47/629 (2022.01); H04L 47/76 (2022.01); H04L 47/762 (2022.01); H04L 47/78 (2022.01); H04L 47/80 (2022.01); H04L 49/00 (2022.01); H04L 49/101 (2022.01); H04L 49/15 (2022.01); H04L 49/90 (2022.01); H04L 49/9005 (2022.01); H04L 49/9047 (2022.01); H04L 67/1097 (2022.01); H04L 69/22 (2022.01); H04L 69/40 (2022.01); H04L 45/28 (2022.01); H04L 45/7453 (2022.01); H04L 69/28 (2022.01)
CPC G06F 13/1642 (2013.01) [G06F 9/505 (2013.01); G06F 9/546 (2013.01); G06F 12/0862 (2013.01); G06F 12/1036 (2013.01); G06F 12/1063 (2013.01); G06F 13/14 (2013.01); G06F 13/16 (2013.01); G06F 13/1673 (2013.01); G06F 13/28 (2013.01); G06F 13/385 (2013.01); G06F 13/4022 (2013.01); G06F 13/4068 (2013.01); G06F 13/4221 (2013.01); G06F 15/17331 (2013.01); H04L 1/0083 (2013.01); H04L 43/0876 (2013.01); H04L 43/10 (2013.01); H04L 45/02 (2013.01); H04L 45/021 (2013.01); H04L 45/028 (2013.01); H04L 45/122 (2013.01); H04L 45/123 (2013.01); H04L 45/125 (2013.01); H04L 45/16 (2013.01); H04L 45/20 (2013.01); H04L 45/22 (2013.01); H04L 45/24 (2013.01); H04L 45/38 (2013.01); H04L 45/42 (2013.01); H04L 45/46 (2013.01); H04L 45/566 (2013.01); H04L 45/70 (2013.01); H04L 45/745 (2013.01); H04L 47/11 (2013.01); H04L 47/12 (2013.01); H04L 47/122 (2013.01); H04L 47/18 (2013.01); H04L 47/20 (2013.01); H04L 47/22 (2013.01); H04L 47/24 (2013.01); H04L 47/2441 (2013.01); H04L 47/2466 (2013.01); H04L 47/2483 (2013.01); H04L 47/30 (2013.01); H04L 47/32 (2013.01); H04L 47/323 (2013.01); H04L 47/34 (2013.01); H04L 47/39 (2013.01); H04L 47/52 (2013.01); H04L 47/621 (2013.01); H04L 47/6235 (2013.01); H04L 47/626 (2013.01); H04L 47/6275 (2013.01); H04L 47/629 (2013.01); H04L 47/76 (2013.01); H04L 47/762 (2013.01); H04L 47/781 (2013.01); H04L 47/80 (2013.01); H04L 49/101 (2013.01); H04L 49/15 (2013.01); H04L 49/30 (2013.01); H04L 49/3009 (2013.01); H04L 49/3018 (2013.01); H04L 49/3027 (2013.01); H04L 49/90 (2013.01); H04L 49/9005 (2013.01); H04L 49/9021 (2013.01); H04L 49/9036 (2013.01); H04L 49/9047 (2013.01); H04L 67/1097 (2013.01); H04L 69/22 (2013.01); H04L 69/40 (2013.01); G06F 13/1689 (2013.01); G06F 2212/50 (2013.01); G06F 2213/0026 (2013.01); G06F 2213/3808 (2013.01); H04L 45/28 (2013.01); H04L 45/7453 (2013.01); H04L 69/28 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A method for facilitating dynamic buffer management in a switch, the method comprising:
reserving a fixed space of an input buffer for each virtual channel of a physical link;
determining a virtual channel and buffer class associated with a received packet on the physical link;
determining one or more active virtual channels;
determining a virtual channel space limit in a shared space of the input buffer corresponding to the virtual channel associated with the received packet by calculating a total amount of dynamic space in the input buffer available to the active virtual channels and a percentage each of the active virtual channels is allowed to take across all possible active virtual channel combinations;
determining one or more active buffer classes;
determining a buffer class space limit in the shared space of the input buffer corresponding to the buffer class associated with the received packet by calculating a total amount of dynamic space in the input buffer available to the active buffer classes and a percentage each of the active buffer classes is allowed to take across all possible active buffer classes combinations; and
storing the received packet in the input buffer subject to the virtual channel space limit and buffer class space limit, the determining of the one or more active virtual channels and the one or more active buffer classes being based on one of existence of a request in an age queue or having outstanding credits for link partner input buffer space.