US 12,450,176 B2
System and method for securing indirect memory accesses
Vivek Singh, Noida (IN); Nikhil Tiwari, New Delhi (IN); and Vishal Gulati, New Delhi (IN)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., Eindhoven (NL)
Filed on Oct. 26, 2022, as Appl. No. 18/049,683.
Claims priority of application No. 202221050049 (IN), filed on Sep. 1, 2022.
Prior Publication US 2024/0078191 A1, Mar. 7, 2024
Int. Cl. G06F 12/00 (2006.01); G06F 12/14 (2006.01)
CPC G06F 12/1441 (2013.01) [G06F 12/1483 (2013.01); G06F 12/1491 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) configured to perform one or more operations that include accessing data stored within a memory that is external to the IC, the integrated circuit comprising:
a first storage circuit configured to store a first look-up table that includes a plurality of rows indicative of a plurality of instruction sequences associated with accessing the data stored within the memory, and a plurality of addresses of the plurality of rows;
a functional circuit configured to perform the one or more operations, wherein performing the one or more operations includes initiating an indirect memory access of the memory by generating a request packet for the indirect memory access, wherein the request packet includes a sequence identifier (ID) that indicates an address;
a security system that is coupled to the functional circuit and to the first storage circuit, and the security system is configured to
receive (i) the request packet from the functional circuit, (ii) a functional identifier (ID) that identifies the functional circuit, and (iii) a security attribute indicative of a security level of the functional circuit,
validate the functional circuit based on the security attribute and the functional ID,
when the functional circuit is successfully validated, identify an instruction sequence associated with the indirect memory access from the plurality of instruction sequences in the first look-up table by matching an address of the plurality of addresses in the first look-up table with the sequence ID in the request packet,
determine, based on the sequence ID, a type of the indirect memory access, wherein the type of the indirect memory access includes an indirect memory access type selected from a write access type and a read access type, and
validate the type of the indirect memory access based on the security attribute and the request packet; and
a memory controller that is coupled to the memory, and, when the type of the indirect memory access is successfully validated, the memory controller is configured to
identify, based on the request packet, the instruction sequence associated with the indirect memory access, and
execute the instruction sequence on the memory, thereby facilitating the indirect memory access for the functional circuit.