US 12,450,166 B2
Caching host memory address translation data in a memory sub-system
Sumangal Chakrabarty, Campbell, CA (US); Prateek Sharma, San Jose, CA (US); Raja V. S. Halaharivi, Gilroy, CA (US); Yoav Weinberg, Toronto (CA); and Di Hsien Ngu, Zhubei (TW)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 10, 2023, as Appl. No. 18/483,790.
Claims priority of provisional application 63/421,659, filed on Nov. 2, 2022.
Prior Publication US 2024/0143515 A1, May 2, 2024
Int. Cl. G06F 12/1081 (2016.01); G06F 13/30 (2006.01)
CPC G06F 12/1081 (2013.01) [G06F 13/30 (2013.01); G06F 2212/6022 (2013.01); G06F 2212/657 (2013.01)] 21 Claims
OG exemplary drawing
 
21. A system comprising:
host interface circuitry comprising a plurality of host interface circuits to interact with a host system; and
an address translation circuit of the host interface circuitry to handle address translation requests from the plurality of host interface circuits, the address translation circuit comprising:
a set of request staging queues to buffer the address translation requests, each address translation request comprising a virtual address and received from one of the plurality of host interface circuits;
a set of reordering buffers to reorder address translations, which are to be supplied to the plurality of host interface circuits, according to an order of corresponding address translation requests received within the set of request staging queues;
a cache coupled to the set of reordering buffers; and
translation logic coupled to the set of request staging queues, the set of reordering buffers, and the cache, the translation logic to:
store, in the cache, a plurality of the address translations associated with the address translation requests; and
reinsert, into the set of reordering buffers, a first address translation from the cache for a subsequent request for the first address translation by a host interface circuit of the plurality of host interface circuits.