| CPC G06F 12/1027 (2013.01) [G06F 12/1009 (2013.01)] | 20 Claims |
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1. A memory management unit, comprising:
a translation lookaside buffer (TLB) configured to cache page table entries (PTEs) including a mapping relationship between a virtual page number and a physical frame number, and further configured to convert a virtual address received from a processor into a physical address of a main memory using the cached PTEs;
a page table walk request queue configured to queue page table walk requests corresponding to a virtual page number included in the virtual address when a TLB miss has occurred; and
one or more page table walkers (PTWs) configured to acquire, based on virtual page numbers of the page table walk requests, a PTE from the main memory, and to convert the virtual page numbers into physical frame numbers using the PTE,
wherein a PTW, selected from among the one or more PTWs, is configured to select, from among the page table walk requests queued in the page table walk request queue, associated page table walk requests having a same base address of corresponding virtual page numbers, to consecutively provide, to the main memory, cache line requests for acquiring PTEs corresponding to the associated page table walk requests, to acquire, from cache lines acquired from the main memory, the PTEs corresponding to the associated page table walk requests, and to provide the acquired PTEs to the TLB.
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