US 12,450,160 B2
Delta predictions for page scheduling
Aliasger Tayeb Zaidy, Seattle, WA (US); David Andrew Roberts, Wellesley, MA (US); Patrick Michael Sheridan, Boulder, CO (US); and Lukasz Burzawa, Seattle, WA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 7, 2024, as Appl. No. 18/737,526.
Application 18/737,526 is a continuation of application No. 17/867,371, filed on Jul. 18, 2022, granted, now 12,007,899.
Claims priority of provisional application 63/250,460, filed on Sep. 30, 2021.
Prior Publication US 2024/0330190 A1, Oct. 3, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/0882 (2016.01); G06F 12/06 (2006.01)
CPC G06F 12/0882 (2013.01) [G06F 12/0646 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
obtaining memory access sequence data, the memory access sequence data identifying one or more memory addresses previously accessed by a processor;
converting the memory access sequence data to a corresponding first set of delta values, the first set of delta values describing differences between addresses of the memory access sequence data;
mapping each of the delta values of the first set of delta values to a corresponding class to produce a first set of class identifiers;
inputting the class identifiers of the first set of class identifiers into a machine-learned model to produce a predicted future class identifier sequence identifying a set of one or more class identifiers representing one or more predicted future class identifiers representing addresses the machine-learned model predicts will be accessed by the processor in a future timeframe, wherein the machine-learning model utilizes a first class identifier of the first set of class identifiers to predict a first predicted class identifier of the predicted future class identifier sequence and utilizes the first predicted class identifier to predict a second predicted class identifier in the predicted future class identifier sequence;
converting each of the predicted class identifiers in the predicted future class identifier sequence to produce a set of predicted addresses; and
reading memory portions corresponding to selected ones of the addresses in the set of predicted addresses from a first memory system and into a second memory system.