US 12,450,155 B1
Memory device and memory control circuit
Ting-Yu Liu, Hsinchu (TW); and Chi-Yu Chen, Hsinchu (TW)
Assigned to MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed by MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed on Apr. 23, 2024, as Appl. No. 18/642,936.
Int. Cl. G06F 12/02 (2006.01)
CPC G06F 12/0246 (2013.01) [G06F 12/0292 (2013.01); G06F 2212/7201 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory control circuit, used for controlling a memory cell array, wherein the memory control circuit comprises:
a storage unit, configured to store a namespace-table, a logical-to-virtual-mapping-table and a virtual-to-physical-block-table; and
a processing circuit, connected to the storage unit;
wherein the processing circuit is configured to;
obtain a mapping group identification according to a namespace identification and a logical address through the namespace-table;
obtain a block group identification and one of a plurality of mapping entries according to the mapping group identification and an offset of the logical address in the mapping group identification through the logical-to-virtual-mapping-table, wherein the offset is a remainder of dividing the logical address by a number of the plurality of mapping entries corresponding to the mapping group identification; and
obtain a physical block number through the virtual-to-physical-block-table.