US 12,450,154 B2
Selection of erase policy in a memory device
Yu-Chung Lien, San Jose, CA (US); Zhongguang Xu, San Jose, CA (US); Peng Zhang, Los Altos, CA (US); and Zhenming Zhou, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Apr. 11, 2024, as Appl. No. 18/633,288.
Claims priority of provisional application 63/464,315, filed on May 5, 2023.
Prior Publication US 2024/0370364 A1, Nov. 7, 2024
Int. Cl. G06F 12/00 (2006.01); G06F 12/02 (2006.01)
CPC G06F 12/0246 (2013.01) [G06F 2212/7205 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
identifying a block of the memory device, the block spanning over a plurality of decks;
determining whether a set of memory cells of the memory device is disposed in a first deck of the block or a second deck of the block, the first deck having a memory reliability metric satisfying a first criterion pertaining to a reliability of a deck, and the second deck having a memory reliability metric not satisfying the first criterion;
selecting, based on the determination, an erase policy for performing an erase operation with respect to the set of memory cells; and
causing the erase operation to be performed with respect to the set of memory cells in accordance with the erase policy.