US 12,450,120 B2
Streaming engine with error detection, correction and restart
Joseph Zbiciak, San Jose, CA (US); and Timothy Anderson, University Park, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on May 24, 2024, as Appl. No. 18/674,108.
Application 18/674,108 is a continuation of application No. 17/408,561, filed on Aug. 23, 2021, granted, now 11,994,949.
Application 17/408,561 is a continuation of application No. 16/808,683, filed on Mar. 4, 2020, granted, now 11,099,933, issued on Aug. 24, 2021.
Application 16/808,683 is a continuation of application No. 16/133,434, filed on Sep. 17, 2018, granted, now 10,592,339, issued on Mar. 17, 2020.
Application 16/133,434 is a continuation of application No. 15/384,355, filed on Dec. 20, 2016, granted, now 10,078,551, issued on Sep. 18, 2018.
Application 15/384,355 is a continuation in part of application No. 14/331,986, filed on Jul. 15, 2014, granted, now 9,606,803, issued on Mar. 28, 2017.
Claims priority of provisional application 61/846,148, filed on Jul. 15, 2013.
Prior Publication US 2024/0320094 A1, Sep. 26, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G06F 9/30 (2018.01); G06F 9/345 (2018.01); G06F 9/38 (2018.01); G06F 11/00 (2006.01); G06F 11/14 (2006.01); G06F 12/0817 (2016.01); G06F 12/0875 (2016.01); G06F 12/0897 (2016.01); G06F 13/38 (2006.01); G06F 13/40 (2006.01)
CPC G06F 11/1076 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); G06F 9/30047 (2013.01); G06F 9/345 (2013.01); G06F 9/383 (2013.01); G06F 9/3836 (2013.01); G06F 9/3891 (2013.01); G06F 11/00 (2013.01); G06F 11/1405 (2013.01); G06F 12/0817 (2013.01); G06F 12/0875 (2013.01); G06F 12/0897 (2013.01); G06F 9/30043 (2013.01); G06F 9/30141 (2013.01); G06F 9/382 (2013.01); G06F 9/3824 (2013.01); G06F 9/3881 (2013.01); G06F 11/10 (2013.01); G06F 13/38 (2013.01); G06F 13/40 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/452 (2013.01); G06F 2212/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a cache memory configured to store a set of data;
an error-detection code generation circuit coupled to the cache memory and configured to generate a first set of error-detection code for the set of data as read from the cache memory; and
a circuit coupled to the error-detection code generation circuit that includes:
a buffer configured to store the set of data and the first set of error-detection code; and
an error-detection circuit coupled to the buffer and configured to, based on the set of data being provided by the buffer to a processor core:
generate a second set of error-detection code for the set of data as read from the buffer; and
compare the first set of error-detection code to the second set of error-detection code.