US 12,450,118 B2
Automatically detecting and correcting memory errors in a secure multi-channel computer
Nils Weiss, Braunschweig (DE); Alexander Priebe, Braunschweig (DE); and Wolfgang Ebeling, Remlingen (DE)
Assigned to Siemens Mobility GmbH, Munich (DE)
Appl. No. 18/684,913
Filed by Siemens Mobility GmbH, Munich (DE)
PCT Filed Jul. 29, 2022, PCT No. PCT/EP2022/071326
§ 371(c)(1), (2) Date Feb. 20, 2024,
PCT Pub. No. WO2023/020807, PCT Pub. Date Feb. 23, 2023.
Claims priority of application No. 10 2021 209 038.9 (DE), filed on Aug. 18, 2021.
Prior Publication US 2025/0130888 A1, Apr. 24, 2025
Int. Cl. G06F 11/00 (2006.01); G06F 11/10 (2006.01)
CPC G06F 11/10 (2013.01) 11 Claims
OG exemplary drawing
 
1. A method for automatically detecting and correcting memory errors in a secure multi-channel computer of a railway system, the method comprising:
providing each channel of the computer with at least one memory facility and storing the same data in parallel in the memory facilities of the channels;
calculating a first check value for data in a sub-region of a first memory facility;
calculating a second check value for the same data in a sub-region of a second memory facility;
comparing the first and second check values with one another;
comparing at least one of the first check value or the second check value with an old check value, if the first and second check values are different;
replacing the data in the sub-region of the first memory facility with the data in the sub-region of the second memory facility, if the second check value corresponds to an old check value; and
replacing the data in the sub-region of the second memory facility with the data in the sub-region of the first memory facility, if the first check value corresponds to an old check value.