| CPC G06F 9/3806 (2013.01) [G06F 9/30072 (2013.01)] | 20 Claims |
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1. A processor, comprising:
a prefetch circuit configured to fetch instructions including a conditional instruction from memory to an instruction cache; and
a prediction circuit configured to:
predict, during fetch of the conditional instruction to the instruction cache, whether the conditional instruction is biased to a condition outcome affecting a data flow for the instruction; and
responsive to a prediction that the conditional instruction is biased, cause the conditional instruction to be executed according to the predicted bias of the conditional instruction.
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