| CPC G06F 9/3802 (2013.01) [G06F 9/3851 (2013.01)] | 33 Claims |

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1. A microprocessor, comprising:
a prediction unit (PRU) that predicts a sequence of fetch blocks (FBlks) in a program instruction stream, wherein a FBlk comprises a sequential run of architectural instructions; and
a macro-op (MOP) cache (MOC) that comprises MOC entries (MEs), wherein a ME holds MOPs into which architectural instructions of one or more FBlks are decoded, wherein an ME comprises a counter;
wherein the PRU is configured to:
receive a detection of a first instance in which execution of an ME caused a need for an abort;
in response to the detection of the first instance, resetting the counter in the ME; and
subsequent to the detection of the first instance:
increment the counter when the PRU predicts the ME is present in the program instruction stream;
invalidate the ME in the MOC in response to detecting a predetermined number of instances in which execution of the ME caused a need for an abort before the counter reaches a threshold; and
retain the ME in the MOC if the counter reaches the threshold before detecting the predetermined number of instances in which execution of the ME caused a need for an abort.
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