US 12,450,065 B2
Global unified interdependent multi-tenant quality-of-service processor scheme
Francesc Guim Bernat, Barcelona (ES)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 22, 2021, as Appl. No. 17/559,969.
Prior Publication US 2023/0195462 A1, Jun. 22, 2023
Int. Cl. G06F 9/30 (2018.01); G06F 9/50 (2006.01); G06F 11/30 (2006.01)
CPC G06F 9/3016 (2013.01) [G06F 9/30018 (2013.01); G06F 9/30038 (2023.08); G06F 9/5077 (2013.01); G06F 11/3051 (2013.01); G06F 2209/501 (2013.01); G06F 2209/508 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A processor comprising:
execution circuitry to execute one or more threads;
a first one or more registers to store a first one or more values to define a tenant hierarchy, wherein at least one of the first one or more values includes a plurality of bitstrings, each of the plurality of bitstrings corresponds to a level in the tenant hierarchy, and the plurality of bitstrings includes at least one bitstring of consecutive ones and at least one bitstring of consecutive zeroes;
a second one or more registers to store a second one or more values to specify a location of a thread corresponding to a tenant within the tenant hierarchy; and
address generation circuitry to include the second one or more values in a request to access a resource, wherein use of the resource is to be monitored or controlled based on the location of the tenant within the tenant hierarchy.