US 12,450,057 B2
Stream engine with element promotion and decimation modes
Joseph Zbiciak, San Jose, CA (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Dec. 19, 2023, as Appl. No. 18/544,619.
Application 18/544,619 is a continuation of application No. 17/544,740, filed on Dec. 7, 2021, granted, now 11,847,453.
Application 17/544,740 is a continuation of application No. 16/782,580, filed on Feb. 5, 2020, granted, now 11,226,818, issued on Jan. 18, 2022.
Application 16/782,580 is a continuation of application No. 15/636,681, filed on Jun. 29, 2017, granted, now 10,572,255, issued on Feb. 25, 2020.
Prior Publication US 2024/0126549 A1, Apr. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 12/0875 (2016.01); G06F 12/0897 (2016.01)
CPC G06F 9/30043 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); G06F 9/3016 (2013.01); G06F 9/3802 (2013.01); G06F 9/3861 (2013.01); G06F 12/0875 (2013.01); G06F 12/0897 (2013.01); G06F 2212/452 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a memory configured to store a first set of data;
a processor core; and
a circuit coupled between the memory and the processor core that includes:
a first register coupled to the memory and configured to receive the first set of data;
a second register; and
a data format circuit coupled between the first register and the second register and configured to:
receive a promotion value and a decimation value;
produce a second set of data based on the first set of data, the promotion value, and the decimation value, by:
determining, based on the promotion value, whether to increase a number of bits used to represent a first data element of the first set of data in the second set of data; and
determining, based on the decimation value, whether to omit a second data element of the first set of data in the second set of data; and
cause the second set of data to be stored in the second register, wherein the circuit is configured to cause the second set of data to be provided to the processor core.