US 12,450,030 B2
Circuitry for performing a multiply-accumulate operation
John P. Lesso, Edinburgh (GB); and John L. Melanson, Austin, TX (US)
Assigned to Cirrus Logic Inc., Austin, TX (US)
Filed by Cirrus Logic International Semiconductor Ltd., Edinburgh (GB)
Filed on Jul. 29, 2021, as Appl. No. 17/388,285.
Prior Publication US 2023/0046369 A1, Feb. 16, 2023
Int. Cl. G06F 7/544 (2006.01); G06F 17/15 (2006.01); H03M 7/26 (2006.01)
CPC G06F 7/5443 (2013.01) [G06F 17/15 (2013.01); H03M 7/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. Circuitry for performing a multiply-accumulate (MAC) operation, the circuitry comprising:
a first multiplexer having a plurality of inputs for receiving a plurality of unary-coded input signals representing operands of the MAC operation and an output for outputting a multiplexer output signal representing a result of the MAC operation; and
a first vector quantizer configured to receive a plurality of weighting signals, each representing a proportion of a computation time period for which a respective one of the unary-coded input signals should be selected by the multiplexer and to output a first selector signal to the multiplexer to cause the multiplexer to select each of the input signals in accordance with the plurality of weighting signals;
wherein the circuitry further comprises an integrator for integrating the multiplexer output signal over a period of time.