US 12,450,016 B2
Corrective reads implementing incremental reads with respect to adjacent wordlines
Dheeraj Srinivasan, San Jose, CA (US); and Luanming Deng, Chengdu (CN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 23, 2023, as Appl. No. 18/125,279.
Claims priority of provisional application 63/323,130, filed on Mar. 24, 2022.
Prior Publication US 2023/0305717 A1, Sep. 28, 2023
Int. Cl. G06F 3/06 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01)
CPC G06F 3/0679 (2013.01) [G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/3418 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array comprising a target cell connected to a target wordline, a first cell connected to a first adjacent wordline adjacent to the target wordline, and a second cell connected to a second adjacent wordline adjacent to the target wordline; and
control logic, operatively coupled with the memory array, to perform operations comprising:
causing a read to be performed with respect to the first cell to obtain an adjacent wordline read result having a first number of bits;
storing a first bit of the adjacent wordline read result to a first primary data cache, and a second bit of the adjacent wordline read result to a secondary data cache;
causing an incremental read to be performed with respect to the second cell to obtain a first incremental read result having a second number of bits that is less than the first number of bits;
storing the first incremental read result to a second primary data cache;
causing a read to be performed on the target cell to obtain a target cell read result; and
storing the target cell read result to a third primary data cache.