US 12,450,012 B2
Memory die stack chip ID-based command structure
Hari Giduturi, Folsom, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 12, 2024, as Appl. No. 18/634,649.
Application 18/634,649 is a continuation of application No. 17/723,773, filed on Apr. 19, 2022, granted, now 11,972,147.
Prior Publication US 2024/0256188 A1, Aug. 1, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a primary memory component configured to receive instructions from a host device and broadcast commands to multiple secondary memory components using an intra-package interface;
a first secondary memory component coupled to the primary memory component; and
a second secondary memory component coupled to the first secondary memory component;
wherein the commands from the primary memory component uniquely address a selected one of the secondary memory components using a message that includes a chip identification field.