| CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0664 (2013.01); G06F 3/0689 (2013.01)] | 20 Claims |
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1. A device, comprising
a processor;
hardware circuitry; and
a firmware that stores instructions executable by the processor;
logic to manage a virtual disk comprising a plurality of arms, each of the arms comprising physical storage on a physical disk;
a cache comprising random access memory (RAM);
instructions stored in the firmware that are executable by the processor to establish the flexible write cache policy;
logic to execute a first plurality of host input-output operations (IO) in write-back mode, based at least in part on the flexible write cache policy; and
logic to execute a second plurality of host IOs in write-though mode, based at least in part on the flexible write cache policy;
wherein:
the logic to execute the first plurality of host IOs in write-back mode comprises hardware circuitry to create a first plurality of parent accelerated IOs (ACIO) from the first plurality of host IOs; and
the logic to execute the second plurality of IOs in write-though mode comprises hardware circuitry to create a second plurality of parent ACIOs from the second plurality of host IOs; and
the device further comprises hardware circuitry to create a set of two or more child ACIOs from at least one of the parent ACIOs.
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