US 12,450,007 B2
Debug interface between a host system and a memory system
Haihong Liu, Shanghai (CN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Appl. No. 17/420,174
Filed by Micron Technology, Inc., Boise, ID (US)
PCT Filed May 6, 2021, PCT No. PCT/CN2021/091866
§ 371(c)(1), (2) Date Jul. 1, 2021,
PCT Pub. No. WO2022/232980, PCT Pub. Date Nov. 10, 2022.
Prior Publication US 2024/0061611 A1, Feb. 22, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0658 (2013.01); G06F 3/0671 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
receive, from a host system, a write buffer command comprising a mode field with a mode value indicating a debug mode, the write buffer command indicating a count value corresponding to a quantity of commands for debug logging, wherein receiving the mode field triggers the debug logging at the memory system;
store information in a debug log in response to the write buffer command, wherein the information corresponds to a set of commands that is in accordance with the count value;
transmit an indication that the debug log has logged the quantity of commands satisfying the count value;
receive, from the host system and in response to the indication, a second command requesting at least a portion of the information stored in the debug log; and
send, to the host system, the portion of the information in response to the second command.