US 12,449,993 B2
Customizable solid-state drive for improved capacity and endurance
Peng Li, Beaverton, OR (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by MICROSOFT TECHNOLOGY LICENSING, LLC, Redmond, WA (US)
Filed on Mar. 30, 2023, as Appl. No. 18/193,161.
Prior Publication US 2024/0329863 A1, Oct. 3, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0634 (2013.01) [G06F 3/0604 (2013.01); G06F 3/064 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computerized system, comprising:
at least one processor; and
computer memory storing computer-useable instructions that, when executed by the at least one processor, cause the at least one processor to perform operations comprising:
establishing communication with a NAND flash device of a solid-state drive, the NAND flash device comprising a plurality of NAND flash dies that comprises a plurality of NAND blocks;
determining a plurality of block types to program the plurality of NAND blocks to;
subsequent to establishing the communication, causing:
programming a first NAND block of the plurality of NAND blocks as a single-level cell (SLC) based on a first block type of the plurality of block types;
programming a second NAND block of the plurality of NAND blocks as a multi-level cell (MLC) based on a second block type of the plurality of block types;
programming a third NAND block of the plurality of NAND blocks as a triple-level (TLC) based on a first third type of the plurality of block types; and
programming a fourth NAND block of the plurality of NAND blocks as a quad-level cell (QLC) based on a fourth block type of the plurality of block types;
generating and storing, in at least one mapping table, a first association designating the first block type of the first NAND block as the SLC, a second association designating the second block type of the second NAND block as the MLC, a third association designating the third block type of the third NAND block as the TLC, and a fourth association designating the fourth block type of the fourth NAND block as the QLC;
determining a bit requirement associated with an operation code indicating a computer operation to be performed by the solid-state drive;
determining based on the bit requirement and the mapping table at least one of the first NAND block, the second NAND, the third NAND block, and the fourth NAND block to perform the operation;
receiving an input indicative of the computer operation to be performed by the solid-state drive;
determining, from the input, an SSD channel ID, a NAND flash device ID, a NAND flash die ID, a NAND block ID, and a block type ID for the NAND block;
determining, from the input, whether the computer operation should be handled by an SLC, MLC, TLC, or QLC; and
directing the computer operation to the first, second, third, or fourth NAND block based on (1) whether the computer operation should be handled by a NAND block classified as the SLC, the MLC, the TLC, or the QLC, and (2) at least one of the SSD channel ID, the NAND flash device ID, the NAND flash die ID, the NAND block ID, or the block type ID for the NAND block.