US 12,449,981 B2
Non-volatile memory that dynamically reduces the number of bits of data stored per memory cell
Liang Li, Shanghai (CN); Jiahui Yuan, Fremont, CA (US); and Loc Tu, San Jose, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Sandisk Technologies, Inc., Milpitas, CA (US)
Filed on Jul. 24, 2023, as Appl. No. 18/357,354.
Claims priority of provisional application 63/477,483, filed on Dec. 28, 2022.
Prior Publication US 2024/0220130 A1, Jul. 4, 2024
Int. Cl. G06F 3/06 (2006.01); G11C 16/34 (2006.01)
CPC G06F 3/0616 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 16/3495 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A non-volatile storage apparatus, comprising:
a group of non-volatile memory cells; and
a control circuit connected to the non-volatile memory cells, the control circuit is configured to:
operate the group of non-volatile memory cells at a first number of bits of data per memory cell;
receive a command to perform a memory operation;
determine whether the group of non-volatile memory cells has undergone more than a minimum number of programming cycles;
in response to determining that the group of non-volatile memory cells has undergone more than the minimum number of programming cycles and the memory operation being a read process, perform the memory operation on the group of non-volatile memory cells at the first number of bits of data per memory cell; and
in response to determining that the group of non-volatile memory cells has undergone more than the minimum number of programming cycles and the memory operation being a programming process, convert the group of non-volatile memory cells to a second number of bits of data per memory cell and operate the group of non-volatile memory cells at the second number of bits of data per memory cell.