| CPC G06F 3/061 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0673 (2013.01)] | 17 Claims |

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1. An integrated circuit, comprising:
memory to store:
one or more virtualization tables comprising resource control descriptors which each correspond to one of a respective process address space identifier (PASID) or a respective domain identifier, the resource control descriptors each to identify a respective one or more quality of service (QOS) requirements; and
a table comprising a first plurality of entries each indexed by a respective PASID; and
an input/output (IO) memory management unit (IOMMU) communicatively coupled to the memory, the IOMMU including circuitry to:
receive an indication of an IO transaction which is to access one or more shared resources;
determine, based on the indication, an identifier of a requester of the IO transaction;
perform a search of the table based on the identifier of the requester, to identify a first entry of the first plurality of entries;
perform an evaluation to determine whether the first entry includes a field that is to provide a pointer to a resource control descriptor;
where the evaluation determines that the first entry includes the field:
determine, based on a value at the field, a first one or more QoS requirements identified by one of the resource control descriptors; and
control a performance of the IO transaction according to the first one or more QoS requirements; and
where the evaluation fails to determine that the first entry includes the field:
determine, based on a domain identifier which corresponds to the requester, a second one or more QoS requirements identified by another of the resource control descriptors; and
control the performance of the IO transaction according to the second one or more QoS requirements.
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