US 12,449,974 B2
Memory compression with improved lookup table scheme
Su Wei Lim, Penang (MY)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Jul. 25, 2024, as Appl. No. 18/784,292.
Claims priority of provisional application 63/537,624, filed on Sep. 11, 2023.
Prior Publication US 2025/0085851 A1, Mar. 13, 2025
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0608 (2013.01) [G06F 3/0644 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory; and
a processing device, operatively coupled with the memory, to perform operations comprising:
partitioning the memory into a plurality of memory partitions, wherein each of the plurality of memory partitions is associated with a corresponding partition identifier;
receiving a host command to access data;
identifying a compression ratio of the data;
identifying a memory partition among the plurality of memory partitions;
identifying a location among a plurality of locations on the memory partition by using a segment identifier and a unit offset address, wherein each of the plurality of locations is associated with a corresponding segment identifier, and wherein the unit offset address is determined in view of a compression ratio range associated with the memory partition; and
performing an operation regarding the data at the identified location on the memory partition.