US 12,449,890 B2
Power saving mode control for a memory instance
Andy Wangkun Chen, Austin, TX (US); Yew Keong Chong, Austin, TX (US); Sriram Thyagarajan, Austin, TX (US); Munish Kumar, Noida (IN); Vivek Asthana, Greater Noida (IN); Andrew John Turner, Cambridge (GB); and Alex James Waugh, Cambridge (GB)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Sep. 26, 2023, as Appl. No. 18/474,400.
Prior Publication US 2025/0103129 A1, Mar. 27, 2025
Int. Cl. G06F 1/26 (2006.01); G06F 1/32 (2019.01); G06F 1/3296 (2019.01); G06F 12/0815 (2016.01)
CPC G06F 1/3296 (2013.01) [G06F 12/0815 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory instance comprising:
a plurality of banks of storage cells to store data values, each bank of storage cells configured to support a power saving mode for retention of the data values in a state in which the storage cells are not readable or writable and power consumption is lower than in an operational mode in which the storage cells are readable and writable;
input/output circuitry shared between the plurality of banks configured to receive write data from external circuitry or to output read data to the external circuitry;
a control interface comprising a plurality of power control signal paths configured to receive power control signals for controlling use of the power saving mode by the plurality of banks;
bank power control circuitry configured to individually control, for each of a plurality of subsets of banks of storage cells within the same memory instance, whether that subset of banks is in the power saving mode based on the power control signals received on the plurality of power control signal paths, wherein for at least one setting for the power control signals, the bank power control circuitry is configured to place one subset of banks of storage cells in the power saving mode while another subset of banks of storage cells is in the operational mode;
coherency control circuitry configured to manage coherency of data cached in private caches of a plurality of processors; and
a shared cache associated with the coherency control circuitry and shared between the plurality of processors, wherein the shared cache includes the memory instance.