| CPC G06F 1/3275 (2013.01) [G06F 1/3225 (2013.01); G11C 5/14 (2013.01); G11C 2207/2227 (2013.01)] | 20 Claims |

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1. A memory system comprising:
a memory device; and
a processing device, operably coupled to the memory device, configured to perform operations comprising:
determining a current pattern of power state change requests received from a host system operably coupled to the memory system by a physical layer interconnect, the physical layer interconnect comprising a Peripheral Component Interconnect Express (PCIe) physical layer, each power state change request being a request for the memory system to enter or exit a power state;
determining whether to activate a reduced power consumption mode on the memory system based on the current pattern, the reduced power consumption mode being different from an individual operation mode associated with an individual power state last requested by the host system, the reduced power consumption mode defining a first set of operation parameters configured to cause the memory system to consume less power than a second set of operation parameters defined by the individual operation mode, the first set of operation parameters causing the memory system to reduce a number of active lanes within the physical layer interconnect; and
in response to determining to activate the reduced power consumption mode, causing the memory system to activate the reduced power consumption mode on the memory system.
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