US 12,449,834 B2
Triggering an error detector on rising and falling edges of clock signals, and generating an error signal therefrom
Youcef Fouzar, Ottawa (CA); Waleed El-halwagy, Ottawa (CA); William Roberts, Highland, UT (US); Kristopher Kshonze, Ottawa (CA); and Faizal Warsalee, Sittsville (CA)
Assigned to Microchip Technology Incorporated, Chandler, AZ (US)
Filed by Microchip Technology Incorporated, Chandler, AZ (US)
Filed on Jun. 13, 2023, as Appl. No. 18/333,827.
Claims priority of provisional application 63/367,581, filed on Jul. 1, 2022.
Prior Publication US 2024/0004420 A1, Jan. 4, 2024
Int. Cl. G06F 1/12 (2006.01); G06F 1/10 (2006.01)
CPC G06F 1/12 (2013.01) [G06F 1/10 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
an error detector;
a first multiplexer including:
an output coupled to a first input of the error detector;
a non-inverting input and an inverting input respectively to receive a first clock signal; and
a select input to receive a control signal;
a second multiplexer including:
an output coupled to a second input of the error detector;
a non-inverting input and an inverting input respectively to receive a second clock signal; and
a select input to receive the control signal; and
a logic circuit separate from the error detector, the logic circuit to:
receive a reset signal of the error detector;
detect a predetermined reset event at least partially based on the reset signal; and
generate the control signal at least partially responsive to the detected reset event.